1. Field of the Invention
The invention relates to a method of fabricating device isolation structures, and more particularly to a method of fabricating shallow trench isolation (STI) structures.
2. Description of the Related Art
Integrated circuits consist of a variety of isolation structures and different device structures and devices are separated by isolation structures, such as shallow trench isolation. Referring to FIG. 1A, a substrate 10 is provided and a pad oxide layer 11 and a nitride layer 12 are formed respectively on the substrate 10. The pad oxide layer 11 and the nitride layer 12 are defined by photolithography and an opening 13 as a trench of STI is formed within the substrate 10 by etching the substrate 10. A liner oxide layer 14 can be formed or not on the surface of the trench. Referring to FIG. 1B, an oxide layer is deposited within the trench by chemical vapor deposition (CVD) and chemical mechanical polishing (CMP) is performed to etch back the oxide layer 15. The nitride layer 12 and the pad oxide layer 11 is then removed and an oxide layer 15a as shown in FIG. 1C is therefore formed.
In the process as described above, wet etching is used to remove the pad oxide layer 11 with hydrofluoric acid solution as an etchant. During isotropic etching, the surface of the oxide layer 15a adjacent the substrate 10 is overetched due to the erosion by the hydrofluoric acid. A recess 16 is thus produced on the sidewall of the trench.
Additionally, a sacrificial oxide layer used to protect the surface of the substrate is typically formed over the surface of the substrate after forming the device isolation region. The sacrificial oxide layer is removed by hydrofluoric acid solution and overetching may still cause a recess on the oxide plug adjacent to the surface of the substrate.
When the semiconductor device is completed, the accumulation of charges occurring in the recess formed on the oxide layer adjacent to the substrate reduces the threshold voltage of the transistor and produces the abnormal sub-threshold current associated with the "kink effect". Occurrence of the kink effect impairs device and circuit performance and is thus undesirable.